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MesbahKarim's avatar
MesbahKarim
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3 years ago

Agilex Ftile is not asserting tx_ready after the reset sequence (tx_rreset/tx_reset_ack)

Hello, I build my controller model to Agilex F-tile transceiver. Please see the configuration below for F-tile and simulation waveform. Xcvr is asserting tx_reset/tx_reset_ack and rx_reset/rx_r...
MesbahKarim's avatar
MesbahKarim
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3 years ago

Hi Goel,

I am using latest released Quartus version 22.4. I can generate only example design of "FHT NRZ 25G 1 PMA lane RSFEC 272/258"

My configuration is closer to "FGT NRZ 50G 2 PMA lanes RSFEC 528/514" but could not run as it did generate support_logic.

My configuration is "FGT NRZ 25G 8 PMA lanes." without RSFEC

Thanks

Mesbah

MesbahKarim's avatar
MesbahKarim
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3 years ago

Sorry, typo it did not generate support_logic

Thanks

Mesbah