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MesbahKarim's avatar
MesbahKarim
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3 years ago

Agilex Ftile is not asserting tx_ready after the reset sequence (tx_rreset/tx_reset_ack)

Hello, I build my controller model to Agilex F-tile transceiver. Please see the configuration below for F-tile and simulation waveform. Xcvr is asserting tx_reset/tx_reset_ack and rx_reset/rx_r...
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


Are you getting tx_reset_ack and rx_reset_ack?


tx_ready will assert when TX PMA and TX datapath are reset successfully and ready for data transfer.


and rx_ready will assert when RX PMA and RX datapath are reset successfully and ready for data transfer, If RX de-skew is disabled.


Note: During F-Tile link initialization, the data pattern sent from the TX has to be scrambled to get rx_ready to assert. If a 0101 pattern or other constant patterns are sent, rx_ready does not assert, and the link does not initialize.


tx_ready and rx_ready will assert when reset has been done successfully.


Thank you

Kshitij Goel


MesbahKarim's avatar
MesbahKarim
Icon for New Contributor rankNew Contributor
3 years ago

Hi Goel,

Yes, I am getting tx_reset_ack and rx_reset_ack.

Could please clarify Red bold part. I am getting tx_reset_ack/rx_reset_ack. Does not it mean TX PMA and TX data path are reset successfully?

tx_ready will assert when TX PMA and TX datapath are reset successfully and ready for data transfer

I am going to run with TX scrambled data pattern to see rx_ready

Thanks

Mesbah