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MesbahKarim's avatar
MesbahKarim
Icon for New Contributor rankNew Contributor
3 years ago

Agilex Ftile is not asserting tx_ready after the reset sequence (tx_rreset/tx_reset_ack)

Hello, I build my controller model to Agilex F-tile transceiver. Please see the configuration below for F-tile and simulation waveform. Xcvr is asserting tx_reset/tx_reset_ack and rx_reset/rx_r...
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


Can you please check are you fulfilling the reset signal requirements? Please refer below link.


https://www.intel.com/content/www/us/en/docs/programmable/683872/22-4-4-3-0/reset-signal-requirements.html


Also, tx_reset and rx_reset input for TX/RX PMAs and TX/RX datapath. Must be kept asserted until tx_reset_ack and rx_reset_ack is asserted. Applies to all TX/RX channels in a F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.


Can you please clarify which Run-Time Reset Sequence you are following.




Thank you

Kshitij Goel