Forum Discussion
Rink
New Contributor
New ContributorAccessing the Global Timer from the FPGA (Cyclone V SoC)?
Is it possible for the FPGA logic side to access the Global Timer? Does it involve a memory-access via the FPGA–to–HPS bridge perhaps? I am interested in capturing the value to resolve event timing...
LeonWaksman
Occasional Contributor
Occasional ContributorNo need send twice the same question. https://forums.intel.com/s/question/0D50P00004Maq4cSAB/accessing-the-global-timer-from-the-fpga-cyclone-v-soc
Leon
RinkNew Contributor
New ContributorSorry - I thought I put it in the wrong section. Only noticed the 'hps' topic at the bottom of the web page after I posted the first one.
