Zero setup relationship in source synchronous output?

I don't like the "system-centric method", but...

In this example your launch clock and latch clock are edge aligned. If the skew is 0, then your clock and data arrive at the destination register at the same time, which is a failure. So there are two choices, either delay the data 90 degrees(in which case you would be shooting for the next latch edge, and your setup would be the next edge like you expect). But it's just as acceptable to delay the clock by 90 degrees, in which case your launch clock and latch clock are the same. For source-synchronous outputs, don't think in traditional terms, as your system rate works best when your clock and data lines are evenly matched.

I'm not doing justice. I posted a document on source-synchronous timing on this forum. Let me know if you can't find it. (I think it's easier, but I'm also obviously biased...)