zero all elements in an array

Right - Im not surprised it doesnt work. MaxPlus2 is a very old program and has a very poor VHDL compiler. Any reason you're using Maxplus 2 (over 10 years old) and not Quartus?

* is not a valid character for VHDL identifiers. You're only allowed letters, numbers and underscore, and it cannot start with a number.

The sensitivity list needs to contain ALL signals that have an influence on process output. So DG and Data are required, as the dx signal needs to change when the data changes. Otherwise in simulation "dx" will appear to behave a like a latch. Synthesis ignores sensitivity lists and builds the circuit as if the process was sensitive to ALL signals unless it is a synchronous process.