Yet another PUF issue.

I appreciate you taking the time to try to model the behavior pletz. I'm pasting the code here, so we can discuss easier.

module BPUFelement(
	excite,
	clk,
	out
);
input	excite;
input   clk;
output	out;
wire net1, net2;
 preset_latch latch_i1 (.clk(clk),.D(net2),.pre(excite),.Q(net1));
 reset_latch latch_i2 (.clk(clk),.D(net1),.clr(excite),.Q(net2));
 
 assign out = net2;
endmodule
module preset_latch (pre,D,Q,clk);
input pre,D,clk;
output Q;
reg reg_int;
always@(pre or D or clk) begin 
 if (clk)
	begin
	 if(pre)
	  reg_int <= 1;
	end  
 else reg_int <= D ;
	
end
assign Q = reg_int;
endmodule
module reset_latch (clk,D,Q,clr);
input clr,D,clk;
output Q;
reg reg_int;
always@(clr or D or clk) begin 
 if (clk)
	begin
	 if(clr)
	  reg_int <= 0;
	end  
 else reg_int <= D ;
	
end
assign Q = reg_int;
endmodule

According to the description in the paper, it seems to me that the circuit follows these rules:

Excite = 1, then drops to 0

CLK = 1, always

if CLK = 1, then Q = D

if PRE = 1, then Q = 1

if CLR = 1, then Q = 0

seems from the code above that only if CLK = 0, then Q = D? Wouldn't it be more accurate to say:

always@(clr or D or clk) begin 
if (clk)
  begin
	if(clr) reg_int <= 0;
	else reg_int <= D ;
  end
end

If I make that change to the preset_latch and reset_latch modules, and run a simulation, I get the following result:

http://img262.imageshack.us/img262/9418/simres1qu3.th.jpg (http://img262.imageshack.us/my.php?image=simres1qu3.jpg)http://img262.imageshack.us/images/thpix.gif (http://g.imageshack.us/thpix.php)

and zoomed in:

http://img262.imageshack.us/img262/337/simres2wc0.th.jpg (http://img262.imageshack.us/my.php?image=simres2wc0.jpg)http://img262.imageshack.us/images/thpix.gif (http://g.imageshack.us/thpix.php)

it seems that the circuit is stabilizing on a particular value, which here happens to be 1. I haven't tried this on a real board yet, but I will later today.