Yet another PUF issue.

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Oh, I see it now. When I directly use the Chip Planner, I get a "Cannot find requested location" error.

So here is another question: when I connect two DFFs in the manner that is described in the paper I get this verilog code:

module BPUFelement(
	stableZero,
	clk,
	excite,
	out
);
input	stableZero;
input	clk;
input	excite;
output	out;
reg	DFF_inst1;
reg	DFF_inst;
assign	out = DFF_inst;
always@(posedge clk or negedge excite or negedge stableZero)
begin
if (!excite)
	begin
	DFF_inst <= 0;
	end
else
if (!stableZero)
	begin
	DFF_inst <= 1;
	end
else
	begin
	DFF_inst <= DFF_inst1;
	end
end
always@(posedge clk or negedge stableZero or negedge excite)
begin
if (!stableZero)
	begin
	DFF_inst1 <= 0;
	end
else
if (!excite)
	begin
	DFF_inst1 <= 1;
	end
else
	begin
	DFF_inst1 <= DFF_inst;
	end
end
endmodule

Won't this always give a result of 0? The paper says to set stableZero to 0, excite to 1, then drop to 0, and clk to 1.

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I tried to model the required behaviour. Look into the Quartus project, maybe it would help you further.