Yet another PUF issue.

--- Quote Start ---

Hi all. I asked some PUF related questions on these boards before, and I am still looking for a good way to implement a PUF on the Altera FPGAs using Quartus II.

So far I've tried:

Race based multiplexer PUFs

Race based carry-chain delay PUF

Race based buffer delay PUF

Ring oscillator based PUF

I'm now trying a new type of PUF called a Butterfly PUF (BPUF). An explanation can be found here:

Fig.3: http://www.cosic.esat.kuleuven.be/publications/article-1154.pdf

My problem is that when I try implementing this PUF, Quartus seems to optimize away the latches. I've solved optimization in the past by including LCELLs or using the "synthesis keep" attribute. How can I make sure the latches are kept? The reason I believe they are removed is that Quartus can't locate them in the floorplan viewer.

Here's my code for the latch:

module Clatch(
	D,
	CLK,
	PRE,
	CLR,
	Q
);
input D;
input CLK;
input PRE;
input CLR;
output Q;
reg latch1 /* synthesis keep*/;
assign	Q = latch1;
always@(posedge CLK or negedge PRE or negedge CLR)
begin
if (!PRE)
	begin
	latch1 <= 1;
	end
else
if (!CLR)
	begin
	latch1 <= 0;
	end
else
	begin
	latch1 <= D;
	end
end
endmodule

--- Quote End ---

Hi,

I setup a project with your code. What is wrong with the result ?