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Altera_Forum
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13 years ago

Xilinx to Altera "DATAPATHONLY" Constraint

I'm converting an Xilinx to Altera and I'm hitting a wall on the following timing constraint. Does Altera have a "DATAPAHTONLY" constraint? NET "clk_125" TNM_NET = FFS "GRP_A"; NET "clk...
Altera_Forum's avatar
Altera_Forum
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13 years ago

In Vivado (X's new software), set_max_delay has a -datapath option which I think does the same as the mue103's constraint.