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binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Xcelium support for Agilex P-tile PCIe simulations

Hi there, I am creating a PCIe controller targeting Agilex F series device. Wanted to run the example design on Cadence Xcelium simulator. When I ran the generated script for Xcelium, I got the belo...
Simulation
  • binupr's avatar
    binupr
    2 years ago

    Hi Wincent,

    Apologies for the delay in responding to your prior follow-up email.

    Yes, you can close this ticket.

    Thank you for the support.

    Regards

    Binu

binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Wei,

Please see my responses marked [Binu]

Question: I also see that the AGI027 Agilex board may be populated with one of 2 devices(AGIB027R29A1E2VR3 or AGIB027R29A1E1VB)

>> I not understand your question, what do you mean by which device gets populated on this board ?

[Binu] I specifically asked this as the FPGA device mentioned in the link has 2 devices mentioned in Table2. The two devices are AGIB027R29A1E2VR3 or AGIB027R29A1E1VB. Table 1 only mentions one device AGIB027R29A1E2VR3. Please see link AGI027 eval kit and below screenshot for reference.

Question: I believe Xcelium will be supported for that device/board as it matches the highlighted item/OPN in below screenshot.

>> Yes, your understanding is correct

[Binu] Today I hit the same error when I tried generating R-Tile IP targeting AGIB027R29A1E2VR3 and ran the Xcelium simulation. I am using Quartus Pro 23.1 and the 23.1 document says this device is supported.

  • xmsim: *F,NOSNAP: Snapshot 'pcie_ed_tb.pcie_ed_tb' does not exist in the libraries.

Hope this clarifies my queries.

Thanks

Binu

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,

    [Binu] I specifically asked this as the FPGA device mentioned in the link has 2 devices mentioned in Table2. The two devices are AGIB027R29A1E2VR3 or AGIB027R29A1E1VB. Table 1 only mentions one device AGIB027R29A1E2VR3. Please see link AGI027 eval kit and below screenshot for reference.

    >> the OPN end with R3 is the latest silicon build, while the other is initial build.
    If you need more information, you can contact the distributor/sales for the product specification.

    [Binu] Today I hit the same error when I tried generating R-Tile IP targeting AGIB027R29A1E2VR3 and ran the Xcelium simulation. I am using Quartus Pro 23.1 and the 23.1 document says this device is supported.

    • xmsim: *F,NOSNAP: Snapshot 'pcie_ed_tb.pcie_ed_tb' does not exist in the libraries.

    >> yes, if refer to the user guide, it shall be supported. Can you please provide me the

    1. Design .qar file

    2. Printscreen of the error
    I will file this to the development team, meanwhile can you try to generate a clean project and try it again if you seeing the same error ?


    Regards,

    Wincent_Intel

    • binupr's avatar
      binupr
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Wincent,

      Thank you for the reply. I cleaned the project but that did not help. But I realised I missed some of the arguments/environment variables mentioned in https://www.intel.com/content/www/us/en/docs/programmable/683544/22-2-6-0-0/simulator-43921.html . Simulation seems to progress and looks like IP component was identified. But simulation was hanging after half an hour. So I kicked off again. Will let you know how that goes.

      Do you know how long the simulation takes? Any ball park figure like 30 minutes, 1hour, 2hour?

      Thanks

      Binu

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        2 years ago

        Hi Binu,

        I check the internal document, by right R-tile with R3 OPN shall able to run simulation and it is supported.
        I do not have the exact simulation time for this, but is shall be less than 2 hours for normal use, however in some case and situation if the design is large, it might take more time.

        Regards,
        Wincent_intel