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Altera_Forum
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8 years ago

Wrong results when running design on hardware

Hello, My design is made of a chain of single work-item kernels transfering data using channels. It runs fine on emulation, and the FPGA binary is built correclty (95% of estimated usage). ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hi HRZ

Thanks for the reply. I overlook that you redefined the int.

For the first one, as far as I know CUDA or OpenCL(GPU) won't run different kernels concurrently unless you specified it with stream, but for Altera FPGA will just launch them concurrently right?

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Just read the Best Practices Guide and it mentioned in AOCL you use different queues to enable concurrent execution and use attribute (blocking) to avoid data race in pipeline.

Another thing I'm wondering is does launching kernels using NDRange for FPGA really execute them in parallel or just pipeline fashion?

One of Altera's online lesson said we should launch kernels in pipeline parallelism, so I assume NDRange is full parallelism, but if that's the case why is the hardware usage already determined when compiling aocx? Because you specify it with attribute?

Sorry for the second question, it should be documented somewhere but I may be using the wrong key word and can't find it. Thanks