Wrong behavior in mixed-HDL simulation

Hi, thanks for your reply.

My UUT is the top-level of the FPGA, so it's fine to have bidirectional pins. I set them to 'H' in my testbench in order to simulate the pull-up resistors on the board.

I'm developing a tiny Secure Digital host, the CMD and DAT lines are bidirectional, while the CLK line goes from the host to the card. CMD and DAT lines are put to 'Z' when they are not used, while the tristate port is enabled when a command, a response, a read or a write is performed.

I found the simulation model of the card online, it was in a very well done project. Moreover, using the breakpoints in Modelsim I verified that it works. It just can't "win" the 'H' in the testbench for some reason.

The code:

sd_host_inst : component sd_host port map (
    ...
    SD_CLK => SD_CLK,
    SD_CMD => SD_CMD,
    SD_DAT => SD_DAT
);

SD_CMD <= 'H';
SD_DAT <= (others => 'H');

sd_card_inst : component sd_card port map (
    SD_CLK => SD_CLK,
    SD_CMD => SD_CMD,
    SD_DAT => SD_DAT
);

Thanks again,

V.