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Altera_Forum
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10 years ago

Writing values into memory and reading those values. Timing Issue!!!

Hi, I am trying to design a memory (logic [7:0] memory [0:31]) in system verilog. First I write 0s into all the address of my memory, then I read one by one. After writing 0 into the address m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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This looks like a software attempt at some hardware. I don't see an array to store any data?

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This is the test bench. I have declared the memory in the design. From the test bench i am giving only the address, data, and other necessary signals.