Writing latches in verilog

HI:

here is my code:

module part4(SW,LEDR,LEDG);

input[2:0] SW;

output[2:0] LEDR;

output[0:0] LEDG;

assign LEDR = SW;

assign Clk = SW[2];

assign R = SW[1];

assign S = SW[0];

wire R_g,S_g,Qa,Qb;/*synthesis keep*/

always @ (posedge Clk);

assign R_g = Clk&R; // R&Clk

assign S_g = Clk&S; // S&Clk

assign Qa = ~(R_g|Qb);

assign Qb = ~(S_g|Qa);

assign LEDG = Qa;

endmodule​

Here are the problems :

1: wire R_g,S_g,Qa,Qb;/*synthesis keep*/

Error: Warning (10885): Verilog HDL Attribute warning at DLatch.v(11): synthesis attribute "keep" with value "1" has no object and is ignored

2: assign Qa = Qb&S_g;

assign Qb = Qa&R_g;

Error: Their value just simply cannot be assigned . The line is red in model sim

Thanks in advance .