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Altera_Forum
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12 years ago

Writing latches in verilog

HI: here is my code: module part4(SW,LEDR,LEDG); input[2:0] SW; output[2:0] LEDR; output[0:0] LEDG; assign LEDR = SW; assign Clk = SW[2]; assign R = SW[1]; ass...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

1. You also cannot make a reg out of a wire. thats what the reg type is for. hence why you cannot keep it.

2. you cannot put an assign inside an always block.