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Altera_Forum
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18 years ago

Writing data to output file VHDL

Hi all, I'm working with a DE2 Altera board Quartus II 6.1 and am trying to take data that I receive from the board, and send it to an output file, a text file. There will be a lot of d...
Altera_Forum's avatar
Altera_Forum
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18 years ago

You are mentioning a DE2 Altera board. Are you trying to do this on hardware or is it a test bench simulation?

What simulator are you using? I know that the ieee.std_logic_textio package is included i ModelSim. I don't know about NCsim and simulation inside Quartus. You might need to install/map additional libraries and packages.

For hardware, the textio packages are simply not synthezisable. What kind of interface is it from the board to where you are trying to write a file?