Honored ContributorI'm considering two options.
The first:
case (address) is
when X"00500" => byte0 <= data;
when X"00501" => byte1 <= data;
when X"00502" => byte2 <= data;
-- and so on
end case;
type big_data is array (0 to 1024) of std_logic_vector(7 downto 0);
signal bytes : big_data;
bytes(address) <= data;
Honored ContributorHave you tried it? Quartus will tell you.
If you end up describing the same function, but in two different way, Quartus may well rationalise it out to the same thing. I'll pick up on a few inconsistencies in your examples. 'address' appears to be 20-bits wide in your fist example, but is 11-bits wide in the second (or did you meant 0 to 1023?). You also refer to 600 registers. I can't see how that's relevant to either option... Cheers, AlexHonored Contributoraddress is 16 bit wide. I meant 0-1023 but actually it'll be about 700 registers.
I suppose the second option faster (it's RAM implementation) but then I should allocate 700 16-bit registers. Waste of memory. Not all of my variables 16-bit wide. In the first option i could write (considering data is 16-bit wide)
case (address) is
when X"00500" => byte <= data;
when X"00501" => bit <= data(0);
when X"00502" => word <= data;
end case;
The second example will infer a ram if the code behaves correcly. I dont know if the first example can infer a ram as byte0/1 etc are separate signals.
Why not try them and see the results?Honored ContributorI see. I'll try.
