Honored Contributorwork/32alu_version01/work.alu32' has no architecture.
I get the error message : '' ** Error: (vsim-3173) Entity 'C:/altera/14.1/work/32alu_version01/work.alu32' has no architecture. '' when I try to simulate the 32 bit Arithmetical Logical Unit .
Could anyone pls tell me why I'm getting this error
Thanks in advance.
here are my .vhd files : (mux2_1.vhd, mux4_1.vhd, full_adder.vhd, alu_1.vhd, alu_32.vhd, mypackage.vhd)
-----mux 2_1.vhd
ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE WORK.mypackage.all;
entity mux2_1 is
port (
i0 : in std_logic;
i1 : in std_logic;
ctr : in std_logic;
q : out std_logic
);
end mux2_1;
architecture mux2_1 of mux2_1 is
begin
m1: process (i0,i1,ctr)
begin
if ctr ='0' then
q <= i0;
else
q <= i1;
end if;
end process m1;
end mux2_1;
-----mux4_1.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE WORK.mypackage.all;
entity mux4_1 is
port ( i0, i1, i2, i3: IN std_logic;
sel: IN std_logic_vector(1 downto 0) ;
q : OUT std_logic);
end mux4_1;
architecture mux4_1 of mux4_1 is
component mux2_1 is
port ( i0,i1,ctr : in std_logic;
q : out std_logic
);
end component;
--ajout des signaux intermedieres x1 et x2
signal x1, x2 :std_logic;
begin
m1: mux2_1
port map(
i0 => i0,
i1 => i1,
ctr =>sel(0),
q => x1
);
m2: mux2_1
port map(
i0 => i2,
i1 => i3,
ctr =>sel(0),
q => x2
);
m3: mux2_1
port map(
i0 => x1,
i1 => x2,
ctr =>sel(1),
q => q
);
end mux4_1;
-----full_adder.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE WORK.mypackage.all;
entity full_adder is
port (
a_add : in std_logic;
b_add : in std_logic;
c_i : in std_logic;
sum : out std_logic;
c_out : out std_logic
);
end full_adder;
architecture full_adder of full_adder is
begin
(c_out,sum) <= unsigned'('0' & a_add) + unsigned'('0' & b_add) + unsigned'('0' & c_i);
end full_adder;
-----alu_1.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE WORK.mypackage.all;
ENTITY alu_1 IS PORT (
a, b, c_in, less : IN STD_LOGIC;
Control : IN STD_LOGIC_VECTOR (3 downto 0);
c_out, result, set: OUT STD_LOGIC
); END alu_1;
ARCHITECTURE alu_1_archi OF alu_1 IS
COMPONENT full_adder
PORT (
a_add, b_add, c_i: IN STD_LOGIC;
sum, c_out: OUT STD_LOGIC
);
end COMPONENT;
COMPONENT mux4_1
PORT ( i0, i1, i2, i3: IN std_logic;
sel: IN std_logic_vector(1 downto 0) ;
q : OUT std_logic);
END COMPONENT;
COMPONENT mux2_1
PORT ( i0, i1, ctr : IN std_logic;
q : OUT std_logic);
end COMPONENT;
--declaration des signaux
signal qmux1 ,qmux2, anot, bnot, a_inv, b_inv, x0, x1, x2 : std_logic;
BEGIN
--completer alu_1
mod1: mux2_1
port map (
i0 => a,
i1 => anot,
ctr => a_inv,
q => qmux1
);
mod2: mux2_1
port map (
i0 => b,
i1 => bnot,
ctr => b_inv,
q => qmux2
);
mod3: full_adder
port map (
a_add => qmux1,
b_add => qmux2,
c_i => c_in,
c_out => c_out,
sum => x2
);
mod4: mux4_1
port map (
i0 => x0,
i1 => x1,
i2 => x2,
i3 => less,
sel(0) => Control(2),
sel(1) => Control(3),
q => result
);
anot <= not a;
bnot <= not b;
a_inv <= Control(0);
b_inv <= Control(1);
x0 <= qmux1 and qmux2;
x1 <= qmux1 or qmux2;
set <= x2;
END alu_1_archi;
-----alu_32.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE WORK.mypackage.all;
ENTITY alu_1 IS PORT (
a, b, c_in, less : IN STD_LOGIC;
Control : IN STD_LOGIC_VECTOR (3 downto 0);
c_out, result, set: OUT STD_LOGIC
); END alu_1;
ARCHITECTURE alu_1_archi OF alu_1 IS
COMPONENT full_adder
PORT (
a_add, b_add, c_i: IN STD_LOGIC;
sum, c_out: OUT STD_LOGIC
);
end COMPONENT;
COMPONENT mux4_1
PORT ( i0, i1, i2, i3: IN std_logic;
sel: IN std_logic_vector(1 downto 0) ;
q : OUT std_logic);
END COMPONENT;
COMPONENT mux2_1
PORT ( i0, i1, ctr : IN std_logic;
q : OUT std_logic);
end COMPONENT;
--signal declaration
signal qmux1 ,qmux2, anot, bnot, a_inv, b_inv, x0, x1, x2 : std_logic;
BEGIN
--completer alu_1
mod1: mux2_1
port map (
i0 => a,
i1 => anot,
ctr => a_inv,
q => qmux1
);
mod2: mux2_1
port map (
i0 => b,
i1 => bnot,
ctr => b_inv,
q => qmux2
);
mod3: full_adder
port map (
a_add => qmux1,
b_add => qmux2,
c_i => c_in,
c_out => c_out,
sum => x2
);
mod4: mux4_1
port map (
i0 => x0,
i1 => x1,
i2 => x2,
i3 => less,
sel(0) => Control(2),
sel(1) => Control(3),
q => result
);
anot <= not a;
bnot <= not b;
a_inv <= Control(0);
b_inv <= Control(1);
x0 <= qmux1 and qmux2;
x1 <= qmux1 or qmux2;
set <= x2;
END alu_1_archi;
-----mypackage.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned. all;
--ENTITY alu_32 IS
--END;
package mypackage is
--ENTITY alu_32 IS
--END;
COMPONENT full_adder
PORT (
a, b, c_in: IN STD_LOGIC;
sum, c_out: OUT STD_LOGIC
);
end COMPONENT;
COMPONENT mux4_1
PORT ( i0, i1, i2, i3: IN std_logic;
sel: IN std_logic_vector(1 downto 0) ;
q : OUT std_logic);
END COMPONENT;
COMPONENT mux2_1
PORT ( i0, i1, ctr : IN std_logic;
q : OUT std_logic);
end COMPONENT;
COMPONENT alu_1
PORT (
a, b, c_in, less : IN STD_LOGIC;
Control : IN STD_LOGIC_VECTOR (3 downto 0);
c_out, result, set: OUT STD_LOGIC
); END COMPONENT;
COMPONENT alu_32
GENERIC (ALU_SIZE: integer := 31);
PORT (
SrcA, SrcB: in std_logic_vector(ALU_SIZE downto 0);
ALUControl : in std_logic_vector (3 downto 0);
c_out: out std_logic;
Resultut std_logic_vector (ALU_SIZE downto 0);
zero: out std_logic
); END component;
end mypackage;
