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Altera_Forum's avatar
Altera_Forum
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13 years ago

Work around for Internal Error: sub-system: SIN?

Hi All:

I have an open service request with Altera on this SR, but double checking with the local experts to see if anyone has see this before. I'm running into the following internal error:

Internal Error: Sub-system: SIN, File: /quartus/tsm/sin/sin_simulation_interface.cpp, Line: 1700

near_target_voltage.is_track_half_vccio() || near_target_voltage.is_track_half_signal_swing() || near_target_voltage.is_double()

I've done the usual work around of deleting the DB directories, and have also tried it in both windows and Linux versions of Quartus. As well as version 11.1 SP1 (latest dp 8) and even the beta of 12.0 (The only difference was the line number of the error went from 1661 to 1700 between 11.1sp1 and beta 12.0)

The design compiles fine for the Cyclone III LS, and I'm trying to validate a pinout for Cyclone V.

If anyone can point me in the correct direction of what this sin_simulation_interface function is working on so I can work around this issue, I would appreciate it. The target device is the 5CGXFC7C6F23I7

Thanks

Pete

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    looks like it might have something to do with a voltage referenced I/O standard. do you have any memory controllers in the design?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    No I don't have any memory controllers today.

    But I did reserve a bunch of pins for an LPDDR interface (1.8 V), expecting to take advantage of the hard memory controller once I figured out how to instantiate it.

    My banks are currently defined today as follows:

    Bank 3A: 3.3v IO (Config and CPU interface)

    Bank 3B: 3.3v IO (CPU interface)

    Bank 4A: 3.3v IO (CPU interface)

    Bank 5A: 3.3v IO (Cpu interface_

    Bank 5B: 2.5v IO (Some BLVDS signals defined)

    Bank 7A: 1.8v IO (Possible Memory Controller plus DDR ADC interface)

    Bank 8A: 1.8v IO (Possibble Memory Controller)

    Bank 9A: 3.3v IO (Config pins based on VCCPGM?)

    Bank GXB_L0 and GXB_L1 (1.1v and 2.5v) (No current logic defined here, but I do have some pins reserved.

    However the error exists even if I remove all pin assignments.

    We are looking into changing the CPU interface from 3.3V down to 1.8V but this is more of a power optimization step that we are still evaluating the significance of the board change to make happen.

    Thanks Pancake..

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Solution:

    Ok I had two lines that somehow got into the QSF that are not supported for Cyclone V: Theses are:

    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise

    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCC"

    I don't know how they got into the QSF, but once I removed the lines the compile now completes as expected. They were not in the normal IO session of the QSF, so I'm thinking they were auto added by the tool at some point.

    Thanks for you help.

    Pete