Will Quartus support generic types?

Hi,

Thanks for the quick reply. You're right, one can use generics to define the width of the std_logic_vector type. But it get's tricky if you want to use records to group signals of your port specification, for example, look at the code again:

library ieee;
use ieee.std_logic_1164.all;
use work.math_pkg.all;
package fifo_pkg is
  type fifo_in_type is record
    data_in : std_logic_vector(DATA_WIDTH_??- 1 downto 0);
    rd      : std_logic;
    wr      : std_logic;
  end record;
  type fifo_out_type is record
    data_out : std_logic_vector(DATA_WIDTH_?? - 1 downto 0);
    empty    : std_logic;
    full     : std_logic;
  end record;
  component fifo is
    generic
      (
        MIN_DEPTH  : integer;
        DATA_WIDTH : integer
        );
    port
      (
        clk   : in  std_logic;
        res_n : in  std_logic;
        i     : in  fifo_in_type;
        o     : out fifo_out_type
        );
  end component fifo;
end fifo_pkg;  

As far as i understood, there is no way to use generics in records in Quartus. So that i could link DATA_WIDTH_?? to DATA_WIDTH from the component declaration. But i could do this with the code i posted in the previous post, so i could instantiate fifos of various width and depth's, and could use records to group the signals.

Sry for not being precise enough when posting this first...

Thanks,

T