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TAnde27's avatar
TAnde27
Icon for New Contributor rankNew Contributor
6 years ago
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Why won't Quartus give me an error or warning for this obvious Verilog error during compilation?

Hi, In my Verilog HDL projects, it seems Quartus provides no notification (errors, warnings, or messages in the compilation log) if I accidentally declare a port as an input but then assign it with...
  • ak6dn's avatar
    ak6dn
    6 years ago

    This is why such tools as 'VeriLint' were developed that try to check the semantics of what your code is doing vs pure syntax.

    Your example has correct language syntax, but the semantics of what you are doing is not (necessarily) meaningful. It could be, or not.

    You can't expect the QuartusII verilog parser to figure these things out. VHDL language is much more strict, Verilog is looser.

AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Tyler,

Quartus can't report logical error.

Modules can be instantiated from within other modules.And can interface with input / output depending on Logic.

The output "y" of bitwise_negation module is connect to input "y" of bitwise_negation_wrapper module.

IT DOES NOT HAVE ANY SYNTAX ERROR.

Check your RTL viewer.

About my example.

I'm connecting q output of first FF using reg net_1 to d input of second FF.

Regards

Anand