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New ContributorWhy won't Quartus give me an error or warning for this obvious Verilog error during compilation?
This is why such tools as 'VeriLint' were developed that try to check the semantics of what your code is doing vs pure syntax.
Your example has correct language syntax, but the semantics of what you are doing is not (necessarily) meaningful. It could be, or not.
You can't expect the QuartusII verilog parser to figure these things out. VHDL language is much more strict, Verilog is looser.
Regular ContributorHi Tyler,
Quartus can't report logical error.
Modules can be instantiated from within other modules.And can interface with input / output depending on Logic.
One question How to create a 2-bit counter?
Please refer module instantiation basic.
Example :Output of one DFF can be input to another.
module dff (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
module top;
reg data, clock;
wire q_out, net_1;
dff inst_1 (.d(data), .q(net_1), .clk(clock));
dff inst_2 (.clk(clock), .d(net_1), .q(q_out));
endmoduleLet me know if this has helped resolve the issue you are facing or if you need any further assistance.
Regards
Anand
TAnde27Yes, but your example is quite different from the one I provided.
In my case, bitwise_negation_wrapper declares an *input* port y which is being internally driven by the instantiated module bitwise_negation. My question is why the compiler isn't complaining about a module driving it's own input port.
I recently read about "port coercion" in Verilog, and that may be what's going on here. Does anyone know if there is a way to have the compiler throw a warning for coerced ports?
