Altera_Forum
Honored Contributor
16 years agoWhy this last unconstrained path?
I am fairly new to TimeQuest, finishing off my first project using it. I almost have a clean report, except for a last unconstrained path which I don't know what to do with.
I have a 50 MHz external clock, which is used for part of the design. A PLL generates a 33 MHz clock which is used for the 2nd part. The 33 MHz clock is also fed out on a port (renamed Clk33_Out). This port is constrained like this: set_max_delay -from [get_ports clk_50] -to [get_ports Clk33_Out] 12. TimeQuest reports a partially constrained port under hold analysis, with an unconstrained path: from PLL_inst|Pll_Clk[0] (that is the 50MHz clk) to Clk33_Out from Clk_50. The setup analysis is clean. The Unconstrained paths > Clock Status Summary shows CLk33 as generated and constrained. What am I missing?