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Altera_Forum
Honored Contributor
13 years agoAnd the right code:
module Tasktest(A,B,clk,C); input [5:0] A,B; input clk; output [5:0] C; always @ (posedge clk) begin Min(A,B,clk,C); end task Min; input [5:0] a,b; input clk; output reg [5:0] min; // begin //always @ (posedge clk); if (a>b) min<=b; else min<=a; end endtask endmodule