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Altera_Forum
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13 years ago

Why the task cannot be synthesisd?

I just try to use a task to improve the programming efficiency. The code is as following: task TwoNumberMin; input [RamWidth-1:0] a,b; input clk; output [RamWidth-1:0] min; always...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I should have taken my own advice! From "Summary of Verilog Syntax" pdf

"6. Tasks & Functions

Tasks and functions in Verilog closely resemble the procedures and functions in programming languages. Both tasks and functions are defined locally in the module in which the tasks and functions will be invoked. No initial or always statement may be defined within either tasks or functions."

It would also be nice if the compiler told us we were not being clever!

For this example a function would probably be the way to go.

++Simon