Why the task cannot be synthesisd?

Try:

task TwoNumberMin;

input [RamWidth-1:0] a,b;

input clk;

output [RamWidth-1:0] min;

begin

always @(posedge clk)

begin

if (a>b)

min<=b;

else

min<=a;

end

end

endtask

I find if there is a problem it is quickest to use a search engine for the construct you are having syntax problems with. In this case: "verilog task" brings up lots of helpful answers.

It would be nice if the error messages from the tools were more helpful too! (Often the error is in the previous line - not the line that gives the error message.)

++Simon