Why the quotient always high resistance state when using the lpm_div

Hi, all,

i have a question on using the lpm_div, and added "lpm" lib to project, but the quotient always high resistance state.

Here is verilog file generated by "MegaWizard Plug-In Manager" tool.

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module LPM_DIV (

clken,

clock,

denom,

numer,

quotient,

remain);

input clken;

input clock;

input [16:0] denom;

input [51:0] numer;

output [51:0] quotient;

output [16:0] remain;

wire [16:0] sub_wire0;

wire [51:0] sub_wire1;

wire [16:0] remain = sub_wire0[16:0];

wire [51:0] quotient = sub_wire1[51:0];

lpm_divide LPM_DIVIDE_component (

.clock (clock),

.clken (clken),

.denom (denom),

.numer (numer),

.remain (sub_wire0),

.quotient (sub_wire1),

.aclr (1'b0));

defparam

LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",

LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",

LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED",

LPM_DIVIDE_component.lpm_pipeline = 1,

LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",

LPM_DIVIDE_component.lpm_widthd = 17,

LPM_DIVIDE_component.lpm_widthn = 52;

endmodule

Then, i have programmed "Testbench" file to test lpm_div module, code is as following.//file name:LPM_DIV_tb.sv

`timescale 1ns/1ns

module LPM_DIV_tb;

reg clk = 0;

reg signed[51:0] numer = 0;

reg [16:0] denom = 0;

wire signed[51:0] quotient;

wire [16:0] remain;

wire clken;

wire clock;

always# 25ns clk = ~clk;

assign clock = clk;

always @(posedge clk)

begin

denom = denom + 1;

numer = numer + numer + denom;

end

assign clken = (denom >= 5);

LPM_DIV LPM_DIV(

.clken(clken),

.clock(clock),

.denom(denom),

.numer(numer),

.quotient(quotient),

.remain(remain));

endmodule

The result simulated by software "Questa Sim" is as following.

https://alteraforum.com/forum/attachment.php?attachmentid=14102&stc=1