Forum Discussion

11000's avatar
11000
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Why the compilation report didn't display the resources usage when I made the verilog file as top file?

I used a PLL to produce clock, but it didn't display the resources usage when I made the verilog file as top file. But when i set the bdf file as top file it worked. Is there any mistakes in my top ...
  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    6 years ago

    Hi 11000,

    Synthesizer removes all logic whose outputs are unused.

    You have have to route out some outputs otherwise the synthesizer will remove all of the logic.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Regards

    Anand

11000's avatar
11000
Icon for New Contributor rankNew Contributor
6 years ago

Hi​ AnandRS，

Thanks to your advice, ​I checked every module 's input and output pins the whole day. At last I made it out by ensuring every module has valid ports. It was really difficult for me to design the top file in verilog while my project had about ten modules. But I also think the bdf file would be complex and unclear in this situation.

Is there any better way for me to design the top file?

Thank you a lot.

AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi 11000,

To view the resource you can add dummy ports in your module and connect it's output ports.

If we do so we can see 1-PLL being used.

Example:

`timescale 1 ps / 1 ps
module top (
		input  wire clk,  
		input  wire  reset,     
		
//dummy ports
		output wire  locked_sig ,
output wire  outclk_0
	);
wire areset_sig ,clk_ms ,clk_ad;
 
PLL	PLL_inst (
	.areset ( areset_sig ),
	.inclk0 ( clk),
	.c0 ( clk_ms ),
	.c1 ( clk_ad ),
	.locked ( locked_sig )
	);
 
endmodule

Regards

Anand