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11000's avatar
11000
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Why the compilation report didn't display the resources usage when I made the verilog file as top file?

I used a PLL to produce clock, but it didn't display the resources usage when I made the verilog file as top file. But when i set the bdf file as top file it worked. Is there any mistakes in my top ...
  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    6 years ago

    Hi 11000,

    Synthesizer removes all logic whose outputs are unused.

    You have have to route out some outputs otherwise the synthesizer will remove all of the logic.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Regards

    Anand

Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Connect the areset input pin to the PLL from the system rst and you can also use an internal wire for the locked pin

wire pll_locked;
 
PLL	PLL_inst (
	.areset ( rst ),
	.inclk0 ( clk0 ),
	.c0 ( clk_ms ),
	.c1 ( clk_ad ),
	.locked ( pll_locked )
	);