Why SIPO works in model sim and not in quartus ?

Question

Hi, i'm trying to make a serial in parallel out (SIPO) shift registrer.

im actually trying to work with the wolfson WM8731 codec on the DE2 board. Here's my problem, btw im pretty new to his.

I have this code that i did in modelsim, simulated it and all, seemed to work.

Then i went in Quartus and tried to make a block from my verilog SIPO and i got a bunch of errors that seem to say my circuit is not synthetizable.

pretty frustating.

so again i'm new to this. can someone tell me what im doing wrong ?

i've included the testbench i use to simulate in modelsim.

thanks in advance !

Lespoils

altera_forum · Answer

Hello, lespoils.

I'm not familiar with Verilog but I think you should add condition [not(cmpt_Fs == Fs)] to statement:

always @(negedge clk) begin

//compteur de coup de clock

cmpt_Size = cmpt_Size+1;

cmpt_Fs = cmpt_Fs+1;

//shift

input_tempdata <= {input_tempdata,serial_in};

end

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