Why is there one cycle delay for a simple counter?

I compiled your design.

If you look at the TimeQuest report we find:

Setup : clk 7.041 0.000

Hold: clk 1.058 0.000

In your .vwf you only have a 5.000 ns setup time for rst_n to clk rising. Hence the design may fail, and the simulator does show so.

I shifted the rst_n signal 2.5 ns to the left, creating 7.5 ns setup time, and the simulator runs fine.

The clock to output is 7.731 ns which makes reading the simulation output a bit difficult.v See the attached image. (I usually use slower clocks even to simulate higher speed designs, just to make setting up and reading signals easier)

You can obtain better setup, hold and clock to output times, but the add proper constraints to your .sdc file.