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Altera_Forum
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15 years ago

Why is there one cycle delay for a simple counter?

The code is as the following: ===================== `timescale 1ns/1ps module counter(clk, rst_n, cnt); input clk; input rst_n; output[3:0] cnt; reg[3:0] cnt; always @(po...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

https://www.alteraforum.com/forum/attachment.php?attachmentid=2850

The archive is attached.

One strange thing is that: I once do the same thing on Quartus 8.1 web edition. If rst_n is low, there is one cycle delay. If rst_n is high, there is NO one cycle delay. It seems that different version has different compiling policy.

Someone told me that I can set constraints to make it work normal. I am a starter on FPGA. Can anyone help to show how to set up constraints? Many thanks.