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Altera_Forum
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15 years ago

Why is there one cycle delay for a simple counter?

The code is as the following: ===================== `timescale 1ns/1ps module counter(clk, rst_n, cnt); input clk; input rst_n; output[3:0] cnt; reg[3:0] cnt; always @(po...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes, you're right. The counter can work at higher clock speeds than 100 MHz, but the rst_n setup time is too short. The 5 ns is exactly at the edge, it happened, that the timing of my simulation waveform was slightly different.