Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Why is there one cycle delay for a simple counter?

The code is as the following: ===================== `timescale 1ns/1ps module counter(clk, rst_n, cnt); input clk; input rst_n; output[3:0] cnt; reg[3:0] cnt; always @(po...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The answer can perhaps be as simple as: the design doesn't work at 100 MHz. The fact that the count reaches 5 was the hint for me.

I usually simulate at lower frequencies (40 MHz or so) just to make life easy on drawing and interpreting the waveforms, otherwise you have to pay attention on the Tsu and Tco times involved.