New ContributorWhy is there no delay in my synthesis results?
I am using Quartus II version 18, and I noticed that tutorial videos on YouTube show delays, but my design does not have any delays. Do I need to use clock constraints, or is there another way to achieve delay that conforms to the setup time and hold time requirements of normal flip-flops?
I kindly request the assistance of experienced individuals to help me with this issue. Thank you in advance.
A functional, RTL simulation will not show delays. I'm not sure what you mean here with two different simulations "function" and "synthesis". They're the same thing. If you want to see delays in a simulation, you have to perform a post-fit, gate-level simulation. But for typical design verification, use RTL simulation along with timing analysis. For that, you need to create timing constraints in a .sdc file.
