Forum Discussion
Altera_Forum
Honored Contributor
18 years agoAlong the same lines, if you are performing gate level timing simulations with Cadence NCsim simulator, the equivalent switches to transport cell and interconnect delays are:
-PULSE_R and -PULSE_INT_R e.g. ncelab work.<my design> -TIMESCALE 1ps/1ps -PULSE_R 0 -PULSE_INT_R