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It doens't look like it is reversed.
Your counters have Most significant bit at lowest number. i.e. row_counter_mod MSB is bit[0].
If you were to look at counter_out[3] logic combo you will find an inverter. This is the normal behavior of a counter which least significant bit toggles every clock(as it is inferred here).
I would infer counters in the opposite order to alleviate making it easy to talk about them as in this case, least significant bit of the counter register is actially most significant bit of the counter.
---------------------
module counter_4(
clk,
counter_out
);
input reg clk;
output reg [3:0] counter_out = 0;
always @ (posedge clk) begin
counter_out <= counter_out + 1;
end
endmodule
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Doh! Its always something simple! Cheers for your response, feeling pretty stupid right now! :oops: Yeh I did figure out that bit [3] had a single inverter, hence it would change state every cycle and act as the LSB. For some reason I thought that the other counters had been inferred the other way and row_counter was different, but on looking at the netlist viewer again, they have all been inferred in the same way, to match the endianness of the statement!
Not quite sure why I adopted the [0:3] notation rather than [3:0], think I was following some SystemVerilog examples that were noted like that a while back. Maybe I need to put Quartus down for a bit and get an early night! ;)
http://www.alteraforum.com/forum/attachment.php?attachmentid=10293&stc=1
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