Why does the fitter generate a counter with a reversed bit order?

It doens't look like it is reversed.

Your counters have Most significant bit at lowest number. i.e. row_counter_mod MSB is bit[0].

If you were to look at counter_out[3] logic combo you will find an inverter. This is the normal behavior of a counter which least significant bit toggles every clock(as it is inferred here).

I would infer counters in the opposite order to alleviate making it easy to talk about them as in this case, least significant bit of the counter register is actially most significant bit of the counter.

---------------------

module counter_4(

clk,

counter_out

);

input reg clk;

output reg [3:0] counter_out = 0;

always @ (posedge clk) begin

counter_out <= counter_out + 1;

end

endmodule

------------------