Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

This is a diagram of the circuit that I would like to build initially. If I get this to work, then there are some other components I would add. This is a time-to-digital-converter (TDC) that uses the embedded, high speed carry chain to measure path delays along paths in the 'logic paths' block (not drawn to scale). The SysClk drives a register on the bottom left that 'launches' a rising edge into 'logic paths' block AND into the delay chain on the right. The 'logic paths' rising edge emerges and then propagates along the carry chain in the adder at high speed. The MPS_path_output drives the clock to the thermometer code registers (declared in Quartus as a Global Clock so the clock tree is used). Once the MPS_path_output goes high, the Thermometer code FFs stop sampling. The MPSsel control bits to the MUX allow different tap points to be selected along the delay chain to account for different delays along the paths in the 'logic paths' block. The idea is to set the MPSsel bits so that the edge propagating along the carry chain is still propagating when the MPS_path_output goes high. This way, you get a sequence of 0's followed by 1's in the Thermometer code FFs. Counting the number of 0's give a relative measure of the delay of the path in the 'logic paths' block that is being measured. In order for this to work, each of the adder cells and corresponding Thermometer code FF must be in the same LE, i.e., routing directly from the LUT to the FF input, and not through a randomly placed buffer as it is doing.

Quartus traces back to MPSsel bit[0] and thinks this signal is a clock. I'd like to tell it that it is NOT a clock and rather the DerivedClkSig is the real clock.