Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

I can try it but the adder and the FFs (from the VHDL code) are in the logic lock region, and the buffers are inserted between the adder and FFs. Clearly the buffers are adding delay to these paths. Why are they being inserted? Are they put in to meet hold time constraints? I've tried several fitter options, e.g., set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" (default is all paths) but nothing seems to work. I'm curious if there is a synthesis or fitter setting that would eliminate them. Alteratively, I could set a tight timing constraint on all of these paths (would be a lot of work) to try to force the tool to leave them out if you think that would be the best (or only) option.