Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

The graphic view I show is from technology map viewer. The downstream connection from the LE buffer is a D input to a FF.

I'm trying to build a time to digital converter and need to place the FF in the same LE as the adder cells. The VHDL is very simple (shown below). The instantiation of this module simply makes the 'a' operand all '0's (128 of them, i.e., TDC_ELEMENTS_NB is 128) and the 'b' operand all '1's except for the low order bit which is driven with a rising transition from a launch register.. The entire 128-bits of the adder are placed in a logic logic region. I seem to find that this 'LE buffer insertion' happens quite often -- all through the design actually. Could it be related to the clocking scheme I'm using? The Clk shown below is actually driven from a FF in my design - I've made the output of the FF a global clock signal in the assignment editor.

entity TDC is

port (

Clk: in std_logic;

RESET: in std_logic;

a: in std_logic_vector(TDC_ELEMENTS_NB-1 downto 0);

b: in std_logic_vector(TDC_ELEMENTS_NB-1 downto 0);

TDC_therm_code: out std_logic_vector(TDC_ELEMENTS_NB-1 downto 0)

);

end entity;

architecture beh of TDC is

signal therm_next, therm_reg : signed (TDC_ELEMENTS_NB downto 0);

begin

process(Clk, RESET)

begin

if ( RESET = '1' ) then

therm_reg <= (others => '1');

elsif ( Clk'event and Clk = '1' ) then

therm_reg <= therm_next;

end if;

end process;

therm_next <= ('0' & signed(a)) + ('0' & signed(b));

TDC_therm_code <= std_logic_vector(therm_reg(TDC_ELEMENTS_NB-1 downto 0));

end beh;