Forum Discussion
gyuunyuu
Contributor
ContributorWhy does Qsys create copies of the source files when it generates a system?
When we "generate" a Qsys system for synthesis (as well as for simulation), Qsys fills in the synthesis and simulation files inside Qsys system folder. Here, it creates copies of RTL files that must ...
KennyT_altera
Super Contributor
Super ContributorIt is the generic values being passed in (parameter in Verilog) are being changed by Qsys.
