Contributor
Super ContributorHere is the more explanation:
let me know if my understanding is not correct. You have your own set of custom RTL which they created _hw.tcl files (QSYS IP) for them to be used within Qsys. They then use Qsys to stitch them together and generate RTL for synthesis/simulation.
The reason why Qsys makes copies is because ultimately, these are "instances" or "variants" of the QSYS IP (_hw.tcl file). The Qsys Infrastructure is designed for this use case to have the capability to define different parameterization for the end-user. we assume your IPs are static RTL; but this was designed for variable RTL that is determined during run-time and such creates RTL for each variant. This is the reason why there seems to be duplicate copies.
ContributorYes, your understanding is correct.
When you say variants, is it that the HDL code itself is being changed or, is it that just the generic values being passed in (parameter in Verilog) are being changed by Qsys?
