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Altera_Forum's avatar
Altera_Forum
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14 years ago

why does ModelSim capture at the same edge

Hi All! Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I would never forward a clock through an entity as it will cause the problem we have been describing (port maps are like signal assignments and add a delta delay). Just connect the clock of the second module to the same clock as the first. ie - all entities on the same level get the same clock input.

This problem wouldnt occur on real hardware because all these clocks refer to the same clock net, but it gets silly in simulation.