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Altera_Forum's avatar
Altera_Forum
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14 years ago

why does ModelSim capture at the same edge

Hi All! Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

hm... this extra assignment is difficult: in this case it cures the problem but in the next stage in my code (the clock is again forwarded with an assignment from input-port to output-port) it causes it again. I need to latch the data directly from the input port to get the desired latched-one-cycle-after-launch behaviour.

Is my assumption right that I need to do all handling on local signals and assign this (incl. the clock) to the output-port to have equal amount of assignments on all data and clock signals?