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Altera_Forum
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14 years ago

why does ModelSim capture at the same edge

Hi All! Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi Tricky! How can I avoid this problem when simulating source synchronous interfaces? I've got the tb clock (clk) which I use to launch the simulation data (ep_*). Then I need to assign this clock to ep_clk to feed the UUT. I can't see how to avoid this assignment.