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Altera_Forum's avatar
Altera_Forum
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14 years ago

why does ModelSim capture at the same edge

Hi All! Currently I'm seeking for understanding why ModelSim 6.6d is capturing my data partly at the following (as expected) and the same edge of the clock: I'm trying to simulate the behaviour ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

are you aware that asignments add 1 delta cycle? so assigning clocks from other clocks can cause the same problem.

was the data input using clk or ep_clk? if you used clk, then it would be 1 delta before ep_clk, and cause the problem you are describing.