Honored Contributor
Honored ContributorMany thanks for all your answers and suggestions.
rbugalho: I'm doing just gate level simulations. dwh: is there any way to force this delay everywhere? Tricky: I'm launching the data using ep_clk (actually an equivalent signal in the testbench). So launch and latch clock are the same. Yesterday I thought I'd found the problem: ep_clk was generated using ep_clk <= clk and nReset, so that ep_* is launched at clk and latched at ep_clk. Unfortunately feeding ep_clk directly by clk does not change the situation. Adding a delay between launch and clock leads to the expected result, data is latched one cycle after launch. What puzzles me most is, that if the launch/latch conditions are unexpected at this point in code, is it the same elsewhere? If so, my simulations results would be quite useless... Is there any way to force more precise evaluation or add a general delay to all data assignments so that latching is always one clock cycle after launch?
