why does ModelSim capture at the same edge

This can be easy to do an annoying when you first see it - but a common problem can be the testbench. Can I guess you have something like this?

ep_clk <= not ep_clk after 10 ns; --or whatever it is for 166MHz
ep_hsync <= '0', '1' after 10ns;

You see the problem is here is that hsync will change at the same time as the clock. BUT - because the rising edge function (and 'event detection) take that extra delta to fire, when local_hsync is assigned it has already changed to '1'.

So, the best thing to do is synchronise the hsync input to the clock in the testbench, and dont use direct time amounts.

process
begin
  ep_hsync <= '0';
  
  wait until rising_edge(ep_clk);
  ep_hsync <= '1';
  wait;
end process;